1. Field of the Invention
This invention relates to semiconductor devices, and more specifically to techniques and structures for testing integrated circuits in flip-chip assemblies.
2. Background of the Invention
Failure analysis is the process of determining the cause of a failure, collecting and analyzing data related to the failure, and developing conclusions to eliminate or mitigate causes of the failure. In the semiconductor industry, conducting failure analysis for integrated circuits is essential to improving the quality and design of the integrated circuits, as well as the manufacturing processes used to produce the integrated circuits. Manufacturers of integrated circuits need to be made aware of weaknesses in their circuits and manufacturing processes in order to develop means for monitoring and eliminating such weaknesses.
Because integrated circuits are incorporated into a wide variety of different electronic packages, performing failure analysis on such integrated circuits can be challenging. For example, as is very common today, multiple integrated circuits, in the form of multiple flip-chip assemblies, may be mounted to a multi-chip module (MCM) substrate. To perform failure analysis for an integrated circuit mounted to such an MCM substrate, the integrated circuit die may be removed from the MCM substrate and attached to a single-chip module (SCM) which is more suitable for testing. However, creating a reliable connection between the integrated circuit die and the SCM substrate after it has been removed from the MCM substrate can be challenging.
One approach for removing an integrated circuit (IC) from an MCM substrate is to cut the MCM substrate around the IC die and grind away the remaining MCM substrate. This will expose the solder interconnects (e.g., C4 interconnects) along with the surrounding underfill material. Solder bumps may then be deposited on the SCM substrate to allow the IC die to be electrically joined to the substrate. Alternatively, solder bumps may be deposited over the interconnects of the IC die to allow the IC die to be electrically joined to the SCM substrate. Unfortunately, these techniques are unreliable as they may cause shorting between the interconnects of the IC die. This shorting may be the result of solder flowing by capillary action into the gap between the IC die and the SCM substrate during the reflow process.
In view of the foregoing, what are needed are improved techniques and structures for testing integrated circuits in flip-chip assemblies. Specifically, improved techniques and structures are needed to rejoin IC dies, removed from existing substrates such as MCM substrates, to new substrates such as SCM substrates.